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Assistance in process
selection
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IC
design from specs to silicon
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RTL design (VHDL,
Verilog)
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Full backend cycle from
RTL to GDS
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Layout design
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Digital content
integration with analog flow and vice versa
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Detail timing analysis
in analog and digital flows
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Support in
design/verification tool setup
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Custom components and
Cell design
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TCL, PERL and other
script languages based design automation
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Design migration to
other process/nodes
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Typeout procedures